The field of the invention is in the solid state transistor art and more particularly in the art of junction field effect transistors in bucket-brigade delay line circuits (JFET BBDL).
It is well recognized that the analysis of the high-speed operating characteristics of a JFET bucket-brigade circuit shows that the charge transfer inefficiency of the device is proportional to the square of the total storage capacitance, C.sub.s. Therefore, for efficient high frequency performance it is important to minimize C.sub.s within the system constraints imposed by processing design rules. In the prior art many innovations have been made to improve the operating characteristics of JFET BBDL circuits. The most applicable prior art, it is believed, may be found in the following U.S. Pat. Nos. 3,639,813 to patentees Kamoshida et al; 3,663,873 to patentee Yagi; 3,784,847 to patentees Kurz et al; 3,790,825 to patentees Barron et al; 3,825,995 to patentees Kurz et al; 3,825,996 to patentees Barron et al; 3,841,917 to patentee Shannon; and 3,896,483 to patentee Whelan.